1. Field of the Invention
The present invention pertains to magnetic domain memory devices and more particularly to a data chip having a dedicated minor loop for storing synchronization and redundancy data.
2. Description of the Prior Art
In recent years tremendous progress has been made in developing equipment for electronic data processing such that today high speed reliable hardware is available to the data processing designer. The newly developed electronic components, particularly those using integrated circuits, have greatly increased the capacity of modern electronic data processing equipment to process data. As the speed and capacity of processing have increased, the data storage requirements have also increased. At present several different techniques exist for storing large quantities of digital data including punched cards, punched tape, magnetic tape, magnetic drums, magnetic disc, and magnetic cores. In all of these types of storage, with the exception of magnetic cores and their solid state storage counterparts, a relatively long period of time is required for accessing any particular bit of data.
On the other hand, with random access type memories such as provided with magnetic cores and their semiconductor counterparts, any particular bit or word stored in the memory can be retrieved extremely fast, the time required to read any stored bit of information being only the time required for the electronic circuits to operate. However, increased speed has also resulted in increased costs. As a consequence, considering in general the memories discussed above, the cost per bit of information stored is cheapest with the slowest devices and most expensive with the fastest devices. Accordingly, there has been an effort to develop large capacity memories which are characterized by a large data access time but which are less expensive than magnetic cores and solid state storage configurations.
In this regard, significant interest has developed recently in a class of magnetic devices generally referred to as magnetic domain devices or "magnetic bubbles". These devices are described, for example, in IEEE Transactions on Magnetics, Vol. MAG - 5, No. 3 (1969), pp. 544-553, "Application of Orthoferrites to Domain - Wall Devices". These magnetic domain devices are generally planar in configuration and are constructed of materials which have magnetically easy directions which are essentially perpendicular to the plane of the structure. Magnetic properties such as magnetization anisotropy, coercivity, and mobility, are such that the device may be maintained magnetically saturated with magnetization in a direction out of the plane and that small localized single domain regions of magnetic polarization aligned opposite to the general polarization direction may be supported. Such localized regions which are generally cylindrical in configuration represent binary memory bits. Interest in these devices in large part is based on the high density that can be obtained and the ability of the cylindrical magnetic domains to be independent of the boundary of the magnetic material in the plane in which it is formed and hence they are capable of moving anywhere in the plane of the magnetic material to effect various data processing operations.
A magnetic domain can be manipulated by programming currents through a pattern of conductors positioned adjacent the magnetic material or by varying the surrounding magnetic field. As an example, the magnetic domains may be formed in thin platelets having uniaxial anisotropy with the easy magnetic axis perpendicular to the plate comprising such material as rare earth orthoferrites, rare earth aluminum and gallium substituted iron garnets and rare earth cobalt or iron amorphous alloys. Since the magnetic bubbles can be propagated, erased, replicated and manipulated to form data processing operations and their presence and absence detected, these bubbles may be utilized to perform the primary functions vital to memory operation.
Many structural organizations of operable magnetic domains have been disclosed in the literature. One of the most popular is the major-minor memory organization disclosed in U.S. Pat. No. 3,618,054. The major-minor loop memory organization as well as its implementation and operation is well known in the art. The major-minor loop organization includes a closed major loop which typically is established by an arrangement of T-bar permalloy circuits on, for example, a rare earth orthoferrite platelet. The magnetic domains are propagated around the loop by in-plane rotating magnetic field action. The major loop is generally elongated to permit a number of minor loops to be aligned along side it. Two way transfer gates permit the transfer of magnetic domains from the minor loop to the major loop and from the major loop to a minor loop. Further access to the major loop is achieved by a detect and read connection thereto and by a separate write connection.
The organization above described permits a synchronized domain pattern since propagation in the loops is synchronous with the rotation of the in-plane field. That is, parallel transfer of data domains from a plurality of minor loops may be made simultaneously to the major loop. Moreover, a plurality of data chips, each with a major loop and a plurality of associated minor loops, may be treated together. It is common to arrange such data chips in rows and then even to stack rows of data chips in time multiplexed layers to achieve complex memory structures, the data domains in all the loops and all the chips being synchronized with in-plane rotations.
Typically, all of the minor loops in the chip, upon command, transfer in parallel the bubbles from their corresponding positions to the major loop. The bubbles are then serially detected as they are propagated past a read position. New data may also be inserted at a write position for parallel transfer back into the minor loops at an appropriate time later (when major loop magnetic domain propagation aligns the data for transfer).
Simultaneous reading/writing of data into a grouping of related major loops gives the capacity of treating related magnetic domains as digital or other coded words. Time multiplexed groups of data chips permits reading and writing of data in a time sharing fashion to permit an overall memory data rate greater than that permitted by magnetic domain propagation in a single chip.
Another structural organization of operable magnetic domains is the block replicate organization, also well known in the art. This organization is presented in an article appearing in AIP Conference Proceedings on Magnetism and Magnetic Materials, No. 29 (1975), pp. 51-53, entitled "64K Fast Access Chip Design". The block replicate organization includes open ended major propagation paths which may be established by an arrangement of T-bar permalloy circuits on, for example, a rare earth orthoferrite platelet. These major propagation paths are aligned adjacent to a plurality of minor loops. Data is written into the minor loops from a major propagation path by way of a swap transfer gate. Old data is transferred into the major propagation paths by a swap signal received from a controller chip and is ultimately annihilated. A subsequent swap signal transfers new data into the minor loops where it becomes non-volatile. To read data out of the minor loops in a block replicate organization it is necessary to read out the magnetic domains onto separate major propagation paths. A replicate gate between the minor loops and the major propagation paths allows the stored data to remain with the minor loops with the data that is read out onto the major propagation path being a replicated version of the stored data. The major distinction between a block replicate organization and a major-minor loop organization is that the data stored within the minor loops remains in the minor loops during the read operation mode in a block replicate while the stored data is transferred completely out onto a major propagation path before replication to a user system in a major-minor loop organization. Also since it is not physically possible to locate the minor loops so as to take advantage of all locations on the major propagation paths, the rate of bubble movement within the respective minor loops is greater than that possible at the detector. In order to overcome this physical disability, the major propagation paths in the block-replicate organization at the output for the reading of the minor loops are merged. Making one major propagation path shorter by one position as compared to another major propagation path allows a merger of the two paths with one path complementing the voids present in the other path. The result of the merger is to double the data rate out of the minor loops to the detector making it equal to the rate within the minor loops.
In both the block replicate organization and the major-minor loop organization, unless special provision is made, every loop in every chip of the system must be perfect for the system to perform satisfactorily. Since chips contain entire groupings of registers, a defect in one of the minor loops would require discarding the entire chip. Various techniques have been proposed in the art for permitting the use of a magnetic domain chip even though one or more of its minor loops may be defective. Exemplary techniques are described, for example, in U.S. Pat. No. 3,909,810 entitled "Bubble Memory Minor Loop Redundancy Scheme", which is assigned to the assignee of the present invention and "Fault-Tolerant Memory Organization: "Impact on Chip Yield and System Cost", IEEE Transactions Magnetics, September, 1974. These techniques utilize separate magnetic domain chips to store locations of defective loops. A further example of a technique to overcome this deficiency is found in pending U.S. Patent Application Ser. No. 594,901 filed July 10, 1975 entitled "Magnetic Domain Minor Loop Redundancy Scheme", now U.S. Pat. No. 4,070,651 issued Jan. 24, 1978 also assigned to the assignee of the present invention. The technique described therein is an important step in development of a system using data chips with defective minor loops. Generally, what is disclosed therein is the use of a non-volatile semiconductor memory, such as a programmable read-only-memory, to store data identifying the relative positions of defective minor loops to each other. This data is used to control logic so that a stream of data bubbles to be transferred into the minor loops for storage, for example, contains intermittent voids corresponding to defective minor loop locations. This latter technique is especially beneficial for storing redundancy data designating defective minor loops in a series of magnetic bubble data chips in a magnetic bubble domain system. A further improvement on this technique is found in pending U.S. Pat. Application Ser. No. 752,947 filed Dec. 17, 1976, entitled "Bubble Redundancy Map Storage Using Non-Volatile Semiconductor Memory" which is also assigned to the assignee of the present invention. This improvement provides for the redundancy data to be stored in an erasable non-volatile semiconductor memory to facilitate magnetic bubble data chip replacement without having to replace the entire array of redundancy data for all data chips within a magnetic domain system.
A further problem found in accessing stored data from a magnetic domain system is the requirement to know at any time the location of specific data stored within the minor loops. In order to be able to locate this data, it is necessary to know when the input or output absolute address in the minor loop and page address in the minor loop containing the data coincide. The minor loop is partitioned into a number of positions capable of supporting and storing magnetic domains, these positions being the absolute addresses of the minor loop. However, the nature of the magnetic domain device is to move individual magnetic domains through each of the positions of the minor loop, and thus each magnetic domain has a page address it retains as it propagates through each absolute address. The absolute address nearest the swap transfer gate may be designated as the input absolute address, while the absolute address nearest to the replicate gate may be designated as the output absolute address. When a user asks for a specific piece of data, although the page address for the data is known, in order to read it out the user must also know at which absolute address it is located so that a control signal can move that page to the appropriate absolute address.